The present invention relates to a device for receiving digital data, and more particularly, to a signal detection circuit for detecting presence/absence of a reception signal.
In serial communications, a signal detection circuit for detecting whether or not a prescribed signal is being input is often used. Such a signal detection circuit determines that an input signal is valid if the absolute value of the voltage of the input signal is equal to or more than a predetermined value and is not valid if the absolute value is less than the predetermined value. In Universal Serial Bus (USB) and Serial AT Attachment (serial ATA), the signal detection circuit is used for a return sequence from an initialize sequence and a power management state. In particular, in Serial ATA, the signal detection circuit is used for detecting an out-of-band (OOB) signal, in addition to detecting the signal state during communications.
The OOB signal is a signal having a fixed-length time period during which a burst signal is transmitted (burst time period) and a non-signal time period repeated alternately, and meaning is given to the lengths of the burst time period and the non-signal time period and the number of times of the repetition. Such an OOB signal is used during initialization and power management.
FIG. 8 is a circuit diagram of a conventional signal detection circuit, which is one described in the Serial ATA standards. The signal detection circuit of FIG. 8 detects whether or not the voltage between input signals DRX and NDRX is equal to or more than a predetermined value, and outputs the detection result as a squelch signal SQOUTA.
FIG. 3 shows an example of the squelch signal obtainable in an ideal case. A squelch signal SQOUT in FIG. 3 goes high in correspondence with the burst time period and goes low during the non-signal time period.
A signal detection circuit that outputs a squelch signal required in USB 2.0 Standard is disclosed in Japanese Laid-Open Patent Publication No. 2003-198392, for example. This circuit has a merit that the input signal is less dependent on a common mode voltage and the allowable voltage range of the input signal is wide.
For a signal detection circuit required to receive a high-frequency signal and respond at high speed, like a signal detection circuit used in Serial ATA and the like, it is necessary to set the voltage used as the reference during detection (threshold value) appropriately considering the signal detection characteristics in high-frequency environments. If the threshold value is not appropriate, the detection result will be as described below.
FIG. 9A is a graph showing a squelch signal generated when the input signals have noise and the threshold value is low. FIG. 9B is a graph showing a squelch signal generated when the input signals have noise and the threshold voltage is high.
If the threshold value is set excessively low in the signal detection circuit of FIG. 8, noise in the input signals DRX and NDRX will be detected erroneously, resulting in output of the squelch signal SQOUTA as the detection result as shown in FIG. 9A. On the contrary, if the threshold voltage is set excessively high, high-frequency components of the input signals DRX and NDRX will fail to be detected, resulting in failure in detection of an input signal although the input signals DRX and NDRX are input, as shown in FIG. 9B.
As another problem, the signal detection circuit is provided with a comparator and transistors constituting the comparator vary in threshold value. Therefore, a given threshold value, if set for signal detection circuits, is not necessarily appropriate, and the detection result may vary among the signal detection circuits.